In this lab, you learn how to verify the functionality of your designs by simulating in Simulink® to ensure that your Vitis Model Composer design is correct when you implement the design in your target Xilinx® device.
Objectives
After completing this lab, you will be able to:
- Identify timing issues in the HDL files generated by Vitis Model Composer and discover the source of the timing violations in your design.
- Perform resource analysis and access the existing resource analysis results, along with recommendations to optimize.
Procedure
This lab has two primary parts:
- In Step 1 you will learn how to do timing analysis in Vitis Model Composer.
- In Step 2 you will learn how to perform resource analysis in Vitis Model Composer.