Step 1: Creating a Design in an FPGA - 2022.1 English

Vitis Model Composer Tutorial (UG1498)
Document ID
UG1498
Release Date
2022-07-25
Version
2022.1 English
In this step, you learn the basic operation of Vitis Model Composer and how to synthesize a Simulink design into an FPGA.
  1. Invoke Vitis Model Composer.
    • On Windows systems, select Windows > Xilinx Design Tools > Vitis Model Composer 2022.1.
    • On Linux systems, type model_composer at the command prompt.
  2. Navigate to the Lab1 folder: \HDL_Library\Lab1.

    You can view the directory contents in the MATLAB® Current Folder browser, or type ls at the command line prompt.

  3. Open the Lab1_1 design as follows:
    1. At the MATLAB command prompt, type open Lab1_1.slx OR
    2. Double-click Lab1_1.slx in the Current Folder browser.

    The Lab1_1 design opens, showing two sine wave sources being added together and passed separately through two low-pass filters. This design highlights that a low-pass filter can be implemented using the Simulink FDATool or Lowpass Filter blocks.



  4. From your Simulink project worksheet, select Simulation > Run or click the Run simulation button.

    When simulation completes you can see the spectrum for the initial summed waveforms, showing a 1 MHz and 9 MHz component, and the results of both filters showing the attenuation of the 9 MHz signals.



    You will now create a version of this same filter using HDL blocks for implementation in an FPGA.

  5. Click the Library Browser button in the Simulink toolbar to open the Simulink Library Browser.

    When using Vitis Model Composer, the Simulink library includes specific blocks for implementing designs in an FPGA. You can find a complete description of the HDL library blocks provided by Vitis Model Composer in the Vitis Model Composer User Guide (UG1483).

  6. Expand the Xilinx Toolbox > HDL menu, select DSP, then select Digital FIR Filter from Non AXI-S.
  7. Right-click the Digital FIR Filter block and select Add block to model Lab1_1.

    You can define the filter coefficients for the Digital FIR Filter block by accessing the block attributes–double-click the Digital FIR Filter block to view these–or, as in this case, they can be defined using the FDATool.

  8. From Xilinx Toolbox > HDL > Tools, select FDATool and add it to the Lab1_1 design.

    An FPGA design requires three important aspects to be defined:

    • The input ports
    • The output ports
    • The FPGA technology

    The next three steps show how each of these attributes is added to your Simulink design.

    Important: If you fail to correctly add these components to your design, it cannot be implemented in an FPGA. Subsequent labs will review in detail how these blocks are configured; however, they must be present in all Vitis Model Composer HDL designs.
  9. In the Interfaces menu, select Gateway In, and add it to the design.

  10. Similarly, from the same menu, add a Gateway Out block to the design.
  11. From the Tools menu, under the HDL menu, add the System Generator token used to define the FPGA technology.
  12. Finally, make a copy of one of the existing Spectrum Analyzer blocks, and rename the instance to Spectrum Analyzer HDL by clicking the instance name label and editing the text.
  13. Connect the blocks as shown in the following figure. Use the left-mouse key to make connections between ports and nets.

The next part of the design process is to configure the HDL blocks.