Step 2: Creating an Optimized Design in an FPGA - 2022.1 English

Vitis Model Composer Tutorial (UG1498)

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2022.1 English
In this step you will see how an FPGA can be used to create a more optimized version of the same design used in Step 1, by oversampling. You will also learn about using workspace variables.
  1. At the command prompt, type open Lab1_2.slx.
  2. From your Simulink project worksheet, select Simulation > Run or click the Run simulation button to confirm this is the same design used in Step 1: Creating a Design in an FPGA.
  3. Double-click the System Generator token to open the Properties Editor.

    As noted in Step 1, the design requires a minimum sample frequency of 18 MHz and it is currently set to 20 MHz (a 50 ns FPGA clock period).

    The frequency at which an FPGA device can be clocked easily exceeds 20 MHz. Running the FPGA at a much higher clock frequency will allow Vitis Model Composer to use the same hardware resources to compute multiple intermediate results.
  4. Double-click the FDATool instance to open the Properties Editor.
  5. Click the Filter Coefficients button to view the filter coefficients.

    This shows the filter uses 11 symmetrical coefficients. This requires a minimum of six multiplications. This is indeed what is shown at the end of the HDL Blocks section where the final hardware is using six DSP48 components, the FPGA resource used to perform a multiplication.

    The current design samples the input at a rate of 20 MHz. If the input is sampled at 6 times the current frequency, it is possible to perform all calculations using a single multiplier.

  6. Close the FDATool Properties Editor.
  7. You will now replace some of the attributes of this design with workspace variables. First, you need to define some workspace variables.
  8. In the MATLAB Command Window:
    1. Enter num_bits = 16
    2. Enter bin_pt = 14

  9. In design Lab1_2, double-click the Gateway In block to open the Properties Editor.
  10. In the Fixed-Point Precision section, replace 16 with num_bits and replace 14 with bin_pt, as shown in the following figure.

  11. Click OK to save and exit the Properties Editor.
    In the System Generator token update the sampling frequency to 120 MHz (6 * 20 MHz) in this way:
    1. Specify an FPGA clock period of 8.33 ns (1/120 MHz).
    2. Specify a Simulink system period of 1/120e6 seconds.
    3. From the Perform analysis menu, select Post Synthesis and from Analyzer type menu, select Resource as shown in the following figure. This option gives the resource utilization details after completion.
    Note: In order to see accurate results from the Resource Analyzer Window it is recommended to specify a new target directory rather than use the current working directory.

  12. Click Generate to compile the design into a hardware description.

    In this case, the message appearing in the Diagnostic Viewer can be dismissed as you are purposely clocking the design above the sample rate to allow resource sharing and reduce resources. Close the Diagnostic Viewer window.

  13. When generation completes, click OK to dismiss the Compilation status dialog box.

    The Resource Analyzer window opens when the generation completes, giving a good estimate of the final design results after synthesis as shown in the following figure.

    The hardware design now uses only a single DSP48 resource (a single multiplier) and compared to the results at the end of the Configure the HDL Blocks section, the resources used are significantly lower.

  14. Click OK to dismiss the Resource Analyzer window.
  15. Click OK to dismiss the System Generator token.
Exit the Lab1_2.slx Simulink worksheet.