- IP catalog
- Hardware Co-Simulation
- Synthesized Checkpoint
- HDL Netlist
- Double-click the
token in the Simulink model. Ensure that the part is specified
and Compilation is set to any one of the compilation targets listed above.Note: In order to see accurate results from Resource Analyzer Window it is recommended to specify a new target directory rather than use the current working directory.
- In the Clocking tab, set the Perform Analysis field to Post
Synthesis and Analyzer type field to
- In the System Generator token dialog box,
Model Comoser processes the resource utilization data and displays a Resource Analyzer window with resource utilization information.
Each column heading (for example, BRAMs, DSPs, or LUTs) in the window shows the total number of each type of resources available in the Xilinx device for which you are targeting your design. The rest of the window displays a hierarchical listing of each subsystem and block in the design, with the count of these resource types.
can cross probe from the Resource Analyzer window to the Simulink model by clicking a block or subsystem
name in the Resource Analyzer window, which highlights the corresponding
Vitis Model Composer HDL block or subsystem in the model.
Cross probing is useful to identify blocks and subsystems that are implemented using a particular type of resource.
- The block you have selected in the window will be highlighted yellow and
outlined in red.
- If the block or subsystem you have selected in the window is within an
upper-level subsystem, then the parent subsystem is highlighted in red in
addition to the underlying block as shown in the following figure.
Important: If the Resource Analyzer window or the Timing Analyzer window opens and no information is displayed in the window (table cells are empty), double-click the System Generator token and set the Target directory to a new directory, that is, a directory that has not been used before. Then run the analysis again.