- Double-click the CodeGen_IP.slx model in the Current Folder.
- Double-click into the Edge Detection subsystem and review the settings on the Interface Spec block. Based on the previous lab, this block has already been set up to map the input and output ports to AXI4-Stream Video interface, and to use the YUV 4:2:2 video format.
- Double-click the Model Composer Hub block, and set the
following in the Block dialog box:
- IP Catalog
- Code directory
- Subsystem name
- To generate an IP from this design, click the Apply button in the Model Composer Hub block dialog box to save
the settings. Then click the Generate
button to start the code generation process.
Vitis Model Composer opens a progress window to show you the status. After completion, click OK and you will see the new codegen_IP/Edge_Detection_prj folder in the Current Folder, which contains the generated IP solution1 folder.
At the end of the IP generation process, Vitis Model Composer opens the Performance Estimates and Utilization Estimates (from the Vitis HLS Synthesis report) in the MATLAB Editor, as shown in the following figures.
You can also see a summary of the generated RTL ports and their associated protocols at the bottom of the report.Note: The actual timing and resource utilization estimates may deviate from above mentioned values, based on the Vitis HLS build you choose.
- Launch Vivado IDE and perform the following steps to add the generated IP to the IP catalog.
- Create a Vivado RTL project.
When you create the Vivado RTL project, specify the Board as Kintex-7 KC705 Evaluation Platform (which is the same as the default Board in the Model Composer Hub block).
- In the Project Manager area of the Flow Navigator pane, click
- From + button and browse to codegen_IP\Edge_Detection_prj\solution1\impl\ip. , click the
- Click Select and see the generated IP get added to the repository.
- Click OK.
- To view the generated Edge_detection IP in the IP catalog, search for
“Edge_Detection”. The generated Edge_detection IP, now appears in the IP catalog
under Vitis HLS IP as shown in the following
You can now add this IP into an IP integrator block diagram, as shown in the following figure.
Using the same example, you will generate an IP from the Edge Detection algorithm.