- Open the Model Composer Hub block dialog box, and set the following:
- HLS C++ code
- Code directory
- Subsystem name
- Click the Apply button on the Model Composer Hub block dialog box to
save the settings and then click the Generate button to
start the code generation process.
- At the end of code generation, observe the Current Folder in MATLAB.
You should now see a new folder: codegen_edge_detection in your Current Folder.
When you click Generate on the Model Composer Hub block, Vitis Model Composer first simulates the model, then generates the code and places the generated code files in the folder that was specified in the Code directory setting. At the end of the code generation process, the window showing the progress of the code generation process tells you where to look for your generated code.
- Open the codegen_edge_detection folder and explore the
generated code files highlighted in the following figure.
- Edge_Detection.cpp is the main file generated for the subsystem.
- run_hls.tcl is the Tcl file needed to create the Vitis HLS project and synthesize the design.
- Navigate back to the directory where the Simulink file
is present, open the Model Composer Hub block dialog box and modify the block
settings as shown in the following figure.
- Check the Create and run testbench check box.
- Modify the Code directory folder.
- Click Apply and regenerate the code
by clicking the Generate and Run button.
Click OK after you see
in the status bar.
You should now see a new folder, codegen_edge_detection2, in your Current Folder.
- Open the codegen_edge_detection2 folder
and explore the generated code files.
With the Create and run testbench option selected on the Model Composer Hub block, Vitis Model Composer logs the inputs and outputs at the boundary of the Edge Detection subsystem and saves the logged stimulus signals in the signals.stim file. The tb.cpp file is the automatically-generated test bench that you can use for verification in Vitis HLS. At the end of the code generation process, Vitis Model Composer automatically verifies that the output from the generated code matches the output logged from the simulation and reports any errors.
In this section you will generate HLS Synthesizable code from the original Edge Detection design. Use the CodeGen_Cplus.slx design for this lab. Simulate the model and ensure that algorithm is functionally correct and gives you the results you would expect.