Choosing IP Catalog as the Target, and clicking Generate, creates a synthesized RTL block that you can directly add to a Vitis Model Composer HDL design using the Vitis HLS block in the HDL Library.
In this lab, you create an IP using Vitis Model Composer HLS Design and then use the synthesized RTL as a block in a Vitis Model Composer HDL design.
- In the HLS_Library\Lab4\HLS_to_HDL
folder, double-click HLS_design.slx to
see the Model Composer HLS design. The design is configured to have AXI4-Stream interfaces at both the input and
output. This is done through the Interface Spec block within the HLS_Design subsystem. Note that there are no
structural changes required at the Simulink
level to change interfaces for the IP.
- Open the followme_script.m in MATLAB. This script will guide you through all the steps to import the Vitis Model Composer HLS generated solution as a block in Vitis Model Composer HDL.
- Read the comments at the start of each section (labeled Section 1 to Section
8) in the MATLAB script and execute each
section one at a time (the start of each section is marked by a
%%sign). You can click on Run and Advance to step through each section in the script. The sections are as follows:
- Section 1: Set up.
Open MATLAB for Vitis Model Composer and choose a video file as an input.
v = VideoReader(video_filename); frame_height = v.Height; frame_width = v.Width; save video_handle v
- Section 2: Creating a Vitis Model
Composer HDL solution from a Vitis
Model Composer HLS design.
Vitis Model Composer allows you to export a HLS design as a block into HDL design. The result of exporting a design from Vitis Model Composer HLS to HDL is a solution folder that you will import into the HDL design using the Vitis HLS block in HDL library.
- Section 3: Serializing the input video.
Serialize the input video which is required for use with the Vitis Model Composer HDL design which will do pixel-based processing.
stream_in = zeros(ceil(v.FrameRate*v.Duration*v.Height*v.Width),1); i = 1; while hasFrame(v) frame = rgb2gray(readFrame(v)); a = reshape(frame',,1); stream_in(i:i+length(a)-1) = a; i = i + length(a); end save stream_in stream_in
- Section 4: Import the generated solution into a Vitis Model Composer HDL design.
Set up the Vitis HLS block in the Vitis Model Composer HDL design to point to the correct solution folder generated in Section 2.
- Section 5: Simulate the Vitis Model
Composer HDL design.
Simulate the Vitis Model Composer HDL design and save the outputs into a MAT file. Note that the simulation will be slower than the Vitis Model Composer HLS design since we are simulating the generated RTL and are doing an element-by-element based processing.
- Section 6: De-serializing the output of the Vitis Model Composer HDL design.
This is a post-processing step that creates a frame-based video for playback using the outputs logged from the Vitis Model Composer HDL simulation.
load stream_out load video_handle disp(['Length of input stream is ',num2str(length(stream_in))]) disp(['Lenght of output stream is ',num2str(length(stream_out))]) outputVideo = VideoWriter('stream_out.avi'); outputVideo.FrameRate = v.FrameRate; open(outputVideo) %The output is boolean. This is why we multiply the img by 255 so that %implay shows the image. for i = 1:length(stream_out)/v.Height/v.Width img = reshape(stream_out((i-1)*v.Height*v.Width+1:i*v.Height*v.Width),v.Width,v.Height); writeVideo(outputVideo,255*img') end close(outputVideo);
- Section 7: Play the de-serialized output using
- Section 1: Set up.
- The AXI4-Stream uses three signals,
READYsignal is a back pressure signal from the slave side to the master side indicating whether the slave side can accept new data.
As you examine the Vitis Model Composer HDL model in Section 4, pay attention to the labels on blocks for each signal to help you understand how the model is designed. For example, whenever the IP can no longer accept input, the
READYsignal (top right of the Vitis HLS block) puts pressure on the master side of the input AXI FIFO by resetting the
READYsignal. Likewise, the input AXI FIFO pressures the input stream by resetting its
READYsignal.Note: In Simulink all the inputs to a block are to one side of the block, and all the outputs are on the opposite side. As such, all the slave or master signals are not bundled together on one side of the block as you might expect.