The NoC provides mechanisms to allocate throughput among different traffic sources in the system. Various Quality of Service (QoS) options are available for read and write traffic. If the throughput is lower than expected, which is usually caused by DRAM efficiency, you can tune the DRAM address map to optimize the DRAM interface for different kinds of traffic. Depending on the traffic class, you can tune the NoC QoS values for each traffic path to meet application needs. For example, you can configure video applications that require a certain bandwidth as isochronous traffic and configure other NoC traffic masters for best effort traffic. For more information, see this link in the Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313). Also see the Vivado Design Tutorials: Versal Network on Chip/DDR Memory Controller Performance Tuning available from the Xilinx GitHub repository.