Traffic analysis comprises mapping the traffic flow from the dynamic random access memory (DRAM) to the Versal ACAP processing hardware blocks using the NoC. All of the following resource blocks in the Versal ACAP can access data from the DRAM using the high-speed NoC interface:
- Processing system (PS)
- Accelerator hardware blocks (like DSPs and AI Engines)
- PCIe interface-based endpoint direct memory access (DMAs)
- High-speed MRMAC blocks
The NoC provides fixed connectivity to embedded hard blocks and programmable connectivity to PL blocks, DSPs, MRMAC (via PL routes), and AI Engines (via PL streams). Each NoC interface is capable of interfacing with an AXI4-based master or slave device that supports memory mapped or streaming transactions.
Following is a traffic analysis example for a PCIe interface-based system that captures the dataflow stages from external host to endpoint device over the PCIe link:
- PCIe interface-based DMAs write the data through the NoC to the DRAM.
- Accelerator block fetches data from the DRAM through the NoC and stores the data in on-chip memory.
- DRAM stores processed data.
- PCIe interface-based DMAs send the data back to the host DDR memory over the PCIe interface.
- Downstream PCIe interface interrupt notifies the host processor about the completion of the data transfer.
Following is a similar example for an embedded system design in which the primary data can originate from an ethernet interface or any secondary storage device:
- Embedded DMA device writes the data through the NoC to the DRAM.
- Accelerator hardware fetches data through the NoC and optionally, stores the data in on-chip memory.
- Data mover block writes the final output data from the accelerator block to the DRAM through the NoC.
- Data mover block notifies the embedded processor about the completion of the data transfer.