Gigabit transceivers (GTs) have specific pinout requirements, and you must consider the following:
- Sharing of reference clocks
- Sharing of PLLs within a quad
- Placement of GT hard blocks, such as PCIe or MRMAC, and their proximity to transceivers
Note: For guidance on GT selection and pin
planning for CPM5, see this link in the
Versal ACAP CPM DMA and Bridge Mode for PCI Express
Product Guide (PG347).
Xilinx recommends that you use the GT wizard to generate the core. Alternatively, you can use the Xilinx IP core for the protocol. Additional I/O pin planning steps are required when using Xilinx transceiver IP. After the IP is customized, assign the top-level transceiver I/O and REFCLK ports to physical package pins in either the elaborated or synthesized design using the Hard Block Planner or Pin Planner in the Vivado IDE. For pinout recommendations, see the related product guide.