To add the Memory IP core to a block design, right-click in the IP integrator design canvas and select Add IP. A searchable IP catalog opens. When you type the first few letters of an IP name, in this case Memory IP, only the IP cores matching the name are listed.
Alternatively, you can click the Add IP button on the toolbar at the top of the canvas .
Double-click to select the Memory Interface Generator IP and add it to your block design.
This places the Memory IP core into the IP integrator block design.
- To make changes to the Memory IP configuration, right-click the block to open
the menu, and click Customize Block. You can also
double-click the Memory IP block to open the Xilinx Memory Interface Generator
The following figure shows both the Memory IP and the 7 series IP core in the upper-left, and the DDR4 Memory IP core for UltraScale devices in the lower-right. The Memory IP that is available in the IP catalog depends on the target part or platform board selected for your project. There are separate IP cores to support DDR3 and DDR4 memory controllers for UltraScale devices.
This example targets the KC705 board for the project. As shown in the following figure, the Board tab of the platform board flow is available to let you select components to interface to your design.
- From the Board tab, drag and drop the DDR3 SDRAM component into
the block design canvas. Note: In the case of the UltraScale KCU105 board, you can also use the DDR4 SDRAM component.
To connect the memory controller to the memory components on the target platform board, the Vivado IP integrator connects the
SYS_CLKand DDR interfaces of the Memory IP to external interface ports, as seen in the following figure.
- Select the Run Connection Automation link at the top of
the design canvas, as seen in the following figure. This connects the Memory IP
to the system FPGA reset on the platform board.
Note: For the KCU105 board, the Run Connection Automation dialog box includes both the
sys_rstinterfaces for the Memory IP.