Enable Barrel Shifter: Enables a hardware barrel shifter in MicroBlaze. This parameter enables the instructions
bsefi. With the 64-bit processor implementation the corresponding long instructions are also enabled. Enabling the barrel shifter can dramatically improve the performance of an application, but increases the size of the processor. The compiler uses the barrel shift instructions automatically if this parameter is enabled.
Enable Floating Point Unit: Enables a
floating point unit (FPU) based on the IEEE-754 standard. Single-precision is
available with the 32-bit processor implementation, and double-precision is added
with the 64-bit implementation. Using the FPU significantly improves the floating
point performance of the application and significantly increases the size of
Setting this parameter to BASIC enables
compareinstructions. Setting it to EXTENDED also enables
square-rootinstructions. The compiler automatically uses the FPU instructions corresponding to setting of this parameter.
Enable Integer Multiplier: Enables a
hardware integer multiplier in MicroBlaze. This parameter enables the instructions
muliwhen set to MUL32.
When set to MUL64, this enables the additional instructions:
mulhsufor 64-bit multiplication. This parameter can be set to NONE to free up
DSP48primitives in the device for other uses. Setting this parameter to NONE has a minor effect on the area of the MicroBlaze processor. When this parameter is enabled, the compiler uses the
Enable Integer Divider: Enables a hardware integer divider in MicroBlaze. This parameter enables the instructions,
idivu. Enabling this parameter can improve the performance of an application that performs integer division, but increases the size of the processor. When this parameter is enabled, the compiler uses the
Enable Additional Machine Status Register Instructions: Enables additional machine status register (MSR) instructions for setting and clearing bits in the MSR. This parameter enables the instructions
msrclr. Enabling this parameter improves the performance of changing bits in the MSR.
Enable Pattern Comparator: Enables
pattern compare instructions
The pattern compare bytes find (
pcmpbf) instructions return the position of the first byte that matches between two words and improves the performance of string and pattern matching operations. The Vitis™ libraries use the
pcmpbfinstructions automatically when this parameter is enabled.
pcmpneinstructions return 1 or 0 based on the equality of the two words. These instructions improve the performance of setting flags and the compiler uses them automatically. With the 64-bit processor implementation, the corresponding long instructions are also enabled.
Selecting this option also enables count leading zeroes instruction,
clzinstruction can improve performance of priority decoding, and normalization.
Enable Reversed Load/Store and Swap Instructions: Enables reversed load/store and swap instructions
swaph. With the 64-bit processor implementation, the long reversed load/store instructions
slrare also enabled. The reversed load/store instructions read or write data with opposite endianness, and the swap instructions allow swapping bytes or half-words in registers. These instructions are mainly useful to improve performance when dealing with big-endian network access with a little-endian MicroBlaze.
Enable Additional Stream Instructions: Provides additional functionality when using AXI4-Stream links, including dynamic access instruction
putdthat use registers to select the interface.
The instructions are also extended with variants that provide:
Important: The extended stream instructions must be enabled to use these additional instructions, and at least one stream link must be selected. The stream exception must be enabled to use instructions that generate stream exceptions.
getdinstructions that generate a stream exception if the control bit is not set
Select Extended Addressing: Set the
memory addressing capability. With the 32-bit processor implementation, this enables
additional load/store instructions to be able to access a larger address space than
4GB (32-bit address). With the 64-bit processor implementation, the extended address
is handled by normal load/store instructions. The data side LMB and AXI bus
addresses are extended to the number of address bits corresponding to the selected
memory size. The available choices are:
- NONE (32-bit address, no additional instructions)
- 64GB (36-bit address)
- 1TB (40-bit address)
- 16TB (44-bit address)
- 256TB (48-bit address)
- 16EB (64-bit address)
- 4PB (52-bit address)
For more information, including software usage and limitations, see the MicroBlaze Processor Reference Guide (UG984).