Manually Creating and Connecting to I/O Ports - 2022.1 English

MicroBlaze Processor Embedded Design User Guide (UG1579)

Document ID
UG1579
Release Date
2022-06-01
Version
2022.1 English

You can manually create external I/O ports in the Vivado IP integrator by connecting signals or interfaces to external I/O ports then selecting a pin, a bus, or an interface connection.

To manually create/connect to an I/O port, right-click the port in the block diagram, and then select one of the following from the right-click menu:

Make External
Use the Ctrl+Click keyboard combination to select multiple pins and invoke the Make External connection. This command ties a pin on an IP to an I/O port on the block design.
Create Port
Creates non-interface signals, such as a clock, reset, or uart_txd. The Create Port option gives more control in terms of specifying the input and output, the bit-width and the type (clk, reset, or data). In case of a clock, you can also specify the input frequency.
Create Interface Port
Creates ports on the interface for groupings of signals that share a common function. For example, the S_AXI is an interface port on several Xilinx IP. The command gives more control in terms of specifying the interface type and the mode (master or slave).