The Vivado® IDE IP integrator is a powerful tool that lets you stitch together a processor-based system.
The MicroBlaze™ embedded processor is a reduced instruction set computer (RISC) core, optimized for implementation in Xilinx® Field Programmable Gate Arrays (FPGAs).
The following figure shows a functional block design of the MicroBlaze core.
The MicroBlaze processor is highly configurable: you can select a specific set of features required by your design. The fixed feature set of the processor includes:
- Thirty-two 32-bit or 64-bit general purpose registers
- 32-bit instruction word with three operands and two addressing modes
- 32-bit address bus, extensible to 64-bits
- Single issue pipeline
In addition to these fixed features, the MicroBlaze processor has parameterized values that allow selective enabling of additional functionality.
See the MicroBlaze Processor Reference Guide (UG984) for more information.
MicroBlaze can be implemented either as a 32-bit processor or a 64-bit processor, depending on user requirements. In general, Xilinx recommends that you select the 32-bit processor implementation unless specific requirements cannot be met. The 64-bit processor extends general-purpose registers to 64 bits, provides additional instructions to handle 64-bit data, and can transparently address instructions and data using up to a 64-bit address. In addition, the floating point unit (FPU) is extended to support double precision.
Another useful document reference is the Triple Modular Redundancy (TMR) LogiCORE IP Product Guide (PG268), which provides soft error detection, correction and recovery for Xilinx devices. The guide describes the IP cores that are part of the solution, and explains typical use cases.