Some Zynq UltraScale+ RFSoCs include highly flexible soft-decision FEC blocks for decoding and encoding data as a means to control errors in data transmission over unreliable or noisy communication channels. The SD-FEC blocks support low-density parity check (LDPC) decode/encode and Turbo decode for use in 5G wireless, backhaul, DOCSIS, and LTE applications.
The SD-FEC is available in ZU21DR and ZU28DR devices. A total of 8 cores can be used for error correction. If you select any of the above mentioned two devices in XPE spreadsheet, a new SD-FEC tab will be added. This sheet can be used for power estimation of SD-FEC.
Use the following inputs to estimate the power: