The Zynq UltraScale+ MPSoC family is based on the Xilinx UltraScale MPSoC architecture. This family of products integrates a feature-rich 64-bit quad-core Arm® Cortex®-A53 and dual-core Arm® Cortex®-R5F based processing system (PS) and Xilinx programmable logic (PL) UltraScale architecture in a single device.
The following configurations as shown in Figure 1 are available for PS Sheet:
- Power Down Mode
- Deep Sleep Mode
- User config mode
- Low Power and Full Power Domains
- You can now select different Full Power and Low Power domain configurations from the PS panel as shown in Figure 2 to Figure 4.
- Processor and PLLs
- The PS for UltraScale+ MPSoC integrates a feature-rich 64-bit quad-core Arm Cortex-A53 for full power and dual-core Arm Cortex-R5F based processing system (PS) for low power domains. It also integrates Xilinx programmable logic (PL) UltraScale architecture in a single device. APU, DDR and Video PLLs are available in full power domain while I/O and RPU PLLs are available in the low power domain.
- Memory and I/O Interfaces
- The Arm Cortex-A53 and Cortex-R5F CPUs also include on-chip memory, external memory interfaces and a rich set of peripheral connectivity interfaces.
- AXI FIFO (AFI) Interfaces
- AXI FIFO Interface of low power domain includes 1 slave and 1 master interfaces. However, full power domain includes 6 slave and 2 master interfaces.