implement_mig_cores - 2022.1 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

Document ID
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2022.1 English

Call IP Services to regenerate an IP, then stitch it into the current netlist


implement_mig_cores [‑output_dir <arg>] [‑rtl_only] [‑force]
    [‑debug_output] [‑quiet] [‑verbose]


Name Description
[-output_dir] Target Output Directory for PHY IP Generated Files Default: empty
[-rtl_only] Run the complete process to generate the PHY RTL code but do not replace the PHY core netlist
[-force] Implement all non-optimized memory cores. When use with -rtl_only, optimized cores will be included, as well.
[-debug_output] Enable debugging output.
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution




Implements the memory IP cores in the current project.

Memory IP included in the Xilinx® IP catalog are used to generate memory controllers and interfaces for Xilinx devices. Memory IP includes different IP cores from the Xilinx IP catalog depending on the device architecture and memory interface specified. Refer to Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions (UG586), or UltraScale Architecture-Based FPGAs Memory Interface Solutions (PG150), for details of the available memory IP.

The implement_mig_cores command generates the RTL information for the physical interface (PHY) of the memory controller, and integrates the synthesized netlist of the memory controller into the top-level design.

A memory controller can be debug enabled when added into the design from the Xilinx IP catalog. In the Vivado® logic analyzer, or the Vivado Lab Edition, memory controllers implemented into a design are associated with hw_mig objects, one hw_mig object per debug-enabled memory controller. The hw_mig object will have all the properties needed to get the calibration status and draw the per-bit eye margin views.

Implementation of the memory IP, and debug core, is automatic when you launch an implementation run using the launch_runs command, or when you run opt_design. However, you can also use the implement_mig_cores command to integrate the memory IP without having to implement the whole design.
Tip: All pins of the memory controller must be assigned prior to running the implement_mig_cores command, or an error will be returned. You can use report_drc to check the status of the memory controller.

This command returns a transcript of its process, or returns an error if it fails.


-output_dir <arg> - (Optional) Specify the output directory for the generated output products of the memory IP. If -outputdir is not specified, the output will be written to the current project folders.

-rtl_only - (Optional) Generate only the PHY RTL information for the memory controller.

-force - (Optional) Force the implementation of the memory IP even if it is up-to-date.

-debug_output - (Optional) Enable the debugging feature of the memory IP.

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.


The following example implements the memory IP cores in the current design: