Optimize dynamic power using intelligent clock gating
power_opt_design [‑quiet] [‑verbose]
|Ignore command errors
|Suspend message limits during command execution
Optimizes the dynamic power consumption of the design by changing clock gating to take advantage of clock enable on a flop. Clock gating optimizations are automatically performed on the entire design to improve power consumption while making no changes to the existing logic or the clocks that would alter the behavior of the design.
You can configure the power optimization to include or exclude specific cells using the
opt_design command. You can disable Block RAM optimization by changing the defaults of
opt_design, or by excluding specific cells from optimization using the
You can also use the
read_saif command prior to optimization, and
power_opt_design will consider the activity data while optimizing the design.
You can run power optimization after synthesis, or after placement. When run before placement, this command optimizes the design to save power. When run after placement, this command optimizes the design to save power while preserving timing. Running after placement limits the optimizations available to the
power_opt_design command. To achieve the best results, the command should be run prior to placement.
-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
opt_design -retarget -propconst -sweep