reset_hw_vio_outputs - 2022.1 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

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2022.1 English

Reset hardware VIO core outputs to initial values.


reset_hw_vio_outputs [‑quiet] [‑verbose] <hw_vios>...


Name Description
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution
<hw_vios> List of hardware VIO objects.




Reset the hardware VIO debug core outputs to their initial, or "reset" state.

The Virtual Input/Output (VIO) debug core can both monitor and drive internal signals on a programmed Xilinx® FPGA in real time. The VIO core uses hardware probes, hw_probe objects, to monitor and drive signals on the device. Input probes monitor signals as inputs to the VIO core. Output probes drive signals to specified values from the VIO core.

The reset_hw_vio_outputs command restores the signal values at the output probes of the specified hw_vio debug cores to their initial values. This affects the signal on the hw_device, but does not affect the OUTPUT_VALUE property of the hw_probe objects.
Tip: This command has the effect of resetting the initial value of the signal on the hw_vio debug core, without resetting the properties on the hw_probe object.

This command returns nothing if successful, or returns an error if it fails.


-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.

<hw_vios> - (Required) Specify one or more hw_vio objects to reset. The hw_vio objects can either be specified as objects returned by the get_hw_vios command, or specified by name.


The following example resets the output probes on the VIO debug core to the initial values on the core when the FPGA was first configured and booted:
reset_hw_vio_outputs [get_hw_vios {hw_vio_1}]