update_design - 2022.1 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

Document ID
Release Date
2022.1 English

update the netlist of the current design


update_design ‑cells <args> [‑strict] [‑from_file <arg>]
    [‑from_design <arg>] [‑from_cell <arg>] [‑black_box] [‑buffer_ports]
    [‑quiet] [‑verbose]


Name Description
-cells List of cells to update with a new sub-netlist.
[-strict] Require exact ports match for replacing cell (otherwise extra ports are allowed).
[-from_file] Name of the file containing the new sub-netlist.
[-from_design] Name of the an open netlist design containing the new sub-netlist.
[-from_cell] Name of cell in the from_design which defines the new sub-netlist.
[-black_box] Update the cell to a black_box.
[-buffer_ports] buffer all the ports of black box
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution




This command updates the in-memory design, replacing the current netlist in the specified cell with a netlist from a specified file, from another open design, from a specified cell of a design, or converts the cell to a black box cell.

The update_design command can update a single instance, or can update all instances of a master cell.

Only the in-memory view of the design is changed by the new netlist. You must save the design using the write_checkpoint command, or any updates will be lost when you close the project or exit the tool.


-cells <args> - (Required) Defines a list of names, or cell objects, to update with the specified netlist.

-strict - (Optional) Require the new netlist to have exactly the same ports as the cell it is imported into. The tool will perform some checking on the new netlist to insure that the specified netlist has all the ports required for the specified cell. However, additional ports are also permitted, unless the -strict option is used.

-from_file - (Optional) Name of a file containing the new netlist. The netlist can be in the form of a structured Verilog netlist (.v) or an EDIF netlist (.edf) file.
Note: -from_file and -from_design are mutually exclusive.

-from_design - (Optional) Allows you to import the netlist from another open design in the current project. The design must be opened in the current tool invocation, and not a separate process.

-from_cell - (Optional) Name of a cell in the design specified with -from_design. The netlist from the specified cell will be used to update the cell in the current design. By default the tool will use the top-level cell of the design specified in -from_design.
Note: This option can only be used with -from_design.

-black_box - (Optional) Change the specified cell into a black box cell.

-buffer_ports - (Optional) Insert buffers for all the ports of a black box cell.

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.


This example replaces a black box cell with the netlist from the specified file:
update_design -from_file C:/Data/cell_contents.v -cell black_box_cell
The following example updates the netlist in the arnd4 cell with the specified Verilog netlist:
update_design -cell arnd4 -from_file C:/Data/round_4.v
The following example updates the arnd4 cell in the current design with the netlist from the same cell in the specified design:
update_design -cell arnd4 -from_design netlist_2 -from_cell arnd4