write_edif - 2022.1 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

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2022.1 English

Export the current netlist as an EDIF file


write_edif [‑pblocks <args>] [‑cell <arg>] [‑force] [‑security_mode <arg>]
    [‑logic_function_stripped] [‑quiet] [‑verbose] <file>


The name of the output file or directory.


Name Description
[-pblocks] Export netlist for these pblocks (not valid with -cell)
[-cell] Export netlist for this cell (not valid with -pblocks)
[-force] Overwrite existing file
[-security_mode] If set to 'all', and some of design needs encryption then whole of design will be written to a single encrypted file Default: multifile
[-logic_function_stripped] Convert INIT strings on LUTs & RAMBs to fixed values
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution
<file> Output file (directory with -pblocks or -cell)




Writes the current netlist as an EDIF file, or outputs the contents of specific Pblocks or hierarchical cells as EDIF netlist files.

In the case of either the -pblocks or -cell option being used, this argument specifies a directory name where the EDIF netlist files for each Pblock or cell will be written. The EDIF netlist file will be named after the Pblock or cell. If the directory specified does not exist, the tool will return an error.


-pblocks <arg> - (Optional) Instructs the tool to output the contents of the specified Pblocks as EDIF netlist files. The contents of each Pblock will be written to a separate EDIF file. These files can be added as design source files to netlist projects, but are not intended to be read into a design using update_design. Use the -cell option to write EDIF netlists for use with update_design.

-cell <arg> - (Optional) Instructs the tool to output the contents of the specified hierarchical cell as EDIF netlist files. Only one cell can be specified for output.

Note: The -pblocks and -cell options are mutually exclusive. Although they are optional arguments, only one can be specified at one time.

-force - (Optional) Overwrite the EDIF file if it already exists.

-security_mode [ multifile | all ] - (Optional) Write a multiple EDIF files when encrypted IP is found in the design, or write a single file.
  • multifile - This is the default setting. By default the command writes out the full design netlist to the specified file. However, if the design contains secured IP, it creates an encrypted file containing the contents of the secured module. This will result in the output of multiple EDIF files, containing secured and unsecured elements of the design.
  • all - Write both encrypted and unencrypted cells to a single specified file.

-logic_function_stripped - (Optional) Hides the INIT values for LUTs & RAMs by converting them to fixed values in order to create a netlist for debug purposes that will not behave properly in simulation or synthesis.

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.
<file> - (Required) The filename of the EDIF file to write. The default file extension for an EDIF netlist is .edn. If the -pblocks or -cell options are used, the name specified here refers to a directory rather than a single file.
Note: If the path is not specified as part of the file name, the file will be written into the current working directory, or the directory from which the tool was launched.


The following example writes an EDIF netlist file for the whole design to the specified file name:
write_edif C:/Data/edifOut.edn
The following example outputs an EDIF netlist for all Pblocks in the design. The files will be written to the specified directory.
write_edif -pblocks [get_pblocks] C:/Data/FPGA_Design/

See Also