Step 7: Implementing the Design - 2022.1 English

Vivado Design Suite Tutorial: Design Flows Overview (UG888)
Document ID
UG888
Release Date
2022-05-05
Version
2022.1 English
  1. Open the create_bft_kintex7_batch.tcl script, or bring the script window to the front.
  2. Individually copy and paste the Tcl commands in the script, in order from opt_design to write_bitstream:
    opt_design
place_design
phys_opt_design
write_checkpoint -force $outputDir/post_place
report_timing_summary -file $outputDir/post_place_timing_summary.rpt
 
route_design
write_checkpoint -force $outputDir/post_route
report_timing_summary -file $outputDir/post_route_timing_summary.rpt
report_timing -sort_by group -max_paths 100 -path_type summary -file \
$outputDir/post_route_timing.rpt
 
report_clock_utilization -file $outputDir/clock_util.rpt
report_utilization -file $outputDir/post_route_util.rpt
report_power -file $outputDir/post_route_power.rpt
report_drc -file $outputDir/post_imp_drc.rpt
 
write_verilog -force $outputDir/bft_impl_netlist.v
write_xdc -no_fixed_only -force $outputDir/bft_impl.xdc
write_bitstream -force $outputDir/bft.bit
  3. Examine each command and notice the various messages produced as the commands are run.
  4. Close the text editor displaying the create_bft_kintex7_batch.tcl script.
  5. Examine the files created in the output directory.

    <Extract_Dir>/Vivado_Tutorial/Tutorial_Created_Data/bft_output

  6. Use a text editor to open the various report (*.rpt) files that were created.
  7. Open the bft_impl.xdc file.
  8. Validate that the design has been implemented with the I/O Port constraint that you modified earlier.