The Vivado Design Suite has several logic simulation options for verifying designs or IP. The Vivado simulator, integrated into the Vivado IDE, allows you to simulate the design, add and view signals in the waveform viewer, and examine and debug the design as needed.
You can use the Vivado simulator to perform behavioral and structural simulation of designs as well as full timing simulation of implemented designs. The previous figure shows all the places where Vivado simulation could be used for functional and timing simulation. You can also use third-party simulators by writing Verilog or VHDL netlists, and SDF files from the elaborated, synthesized, or implemented design. The Vivado IDE lets you configure and launch simulators from Mentor Graphics, Synopsys, Cadence, and Aldec. For more information, see this link in the Vivado Design Suite User Guide: Logic Simulation (UG900).