The Sources window (shown in the following figure) allows you to manage project source files, including adding, removing, and reordering the sources to meet specific design requirements. The Sources window displays the following sources when they are part of the project:
- Design sources
- Constraint files
- Simulation sources
- IP cores
Generally, the Sources window is available in the Vivado IDE whenever a project is open. To open the Sources window, select . The Sources window includes the following folders:
- Design Sources
- Displays source file types, including Verilog, VHDL, NGC/NGO, EDIF, IP cores,
digital signal processing (DSP) modules, and XDC and SDC constraint files.
- Syntax Error Files
- Displays files with syntax errors that affect the design hierarchy.
- Non-Module Files
- Displays files that produced issues during parsing.
- Disabled Sources
- Displays disabled files.
- Displays text files that are part of the project.Note: NGC format files are not supported in the Vivado Design Suite for UltraScale™ devices. Xilinx recommends that you regenerate the IP using the Vivado Design Suite IP customization tools with native output products. Alternatively, you can use the NGC2EDIF command to migrate the NGC file to EDIF format for importing, as described in this link in the ISE to Vivado Design Suite Migration Guide (UG911). However, Xilinx recommends using native Vivado IP rather than XST-generated NGC format files going forward.
- Displays constraint files, which are assigned to constraint sets. For more information on design constraints, see the Vivado Design Suite User Guide: System-Level Design Entry (UG895) and Vivado Design Suite User Guide: Using Constraints (UG903).
- Simulation Sources
- Displays the source files that are used for simulation. For more information on defining and using simulation files, see the Vivado Design Suite User Guide: Logic Simulation (UG900).