In Non-Project Mode, you can perform elaboration of the RTL. You can also cross probe back to the
RTL and run DRCs. Cross probing requires that you load the Vivado
IDE using the
start_gui Tcl command. You can perform DRCs with or
without the Vivado IDE.
Following is a script that sources various files and elaborates the RTL using the
synth_design Tcl command with the
-rtl option. The
script also loads the Vivado IDE so you can cross probe back to the
RTL source from the schematic or netlist.
# create_bft_batch.tcl # bft sample design # A Vivado script that demonstrates a very simple RTL-to-bitstream batch flow # # NOTE: typical usage would be "vivado -mode tcl -source create_bft_batch.tcl" # # STEP#0: define output directory area. # set outputDir ./Tutorial_Created_Data/bft_output file mkdir $outputDir # # STEP#1: setup design sources and constraints # read_vhdl -library bftLib [ glob ./Sources/hdl/bftLib/*.vhdl ] read_vhdl ./Sources/hdl/bft.vhdl read_verilog [ glob ./Sources/hdl/*.v ] read_xdc ./Sources/bft_full.xdc # # STEP #2 Elaborate the RTL and start the GUI for interaction # synth_design -top bft -part xc7k70tfbg484-2 -rtl start_gui # Use stop_gui to quit the GUI and return back to the Vivado IDE Tcl command line