You can perform clock resource and I/O planning early in the design cycle by creating an empty I/O planning project. You can define I/O ports within the Vivado IDE or import them with either comma separated value (CSV) or XDC input files. You can also create empty I/O planning projects to explore the logic resources available on the different device architectures.
After I/O assignment, the Vivado IDE can create CSV, XDC, and RTL output files for use later in the design flow when RTL sources or netlists are available. The output files can also be used to create schematic symbols for use in the printed circuit board (PCB) design process.
Certain types of IP, such as Memory, GT, PCIe® , and Ethernet interfaces have I/O ports associated with them. These IP need to be configured in a Manage IP project, or a RTL project. See the Migrating to an RTL Design section in the Vivado Design Suite User Guide: I/O and Clock Planning (UG899) and Clock Planning for IP with I/O Ports for more information.