For Xilinx target reference platforms or evaluation boards, IP has knowledge of the FPGA pins that are used on the target boards. This is called board awareness. Based on that information, the IP integrator board/connection automation feature can assist you in tying the IP interfaces/ports to external ports on the board. IP integrator then creates the appropriate physical constraints and other I/O constraints required for the I/O port in question.
Current list of IPs that are board aware:
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Note: The IPs in the list are board aware for
one or more boards based on the BOARD.ASSOCIATED_PARAM parameter of the IP's
component.xml on every target board.