The following are attributes and <tags> of the <interface>.
|Indicates the logical direction of the interface. Typically, the mode will be set to "master", but in cases like clocks and reset where the logical direction is for the signals to be input to the FPGA, the mode is marked as "slave".
|A unique name to identify the interface definition in the board file. This name will also be used to drive connection automation, and be seen on the connected port in the block diagram.
Specifies the type of the interface from a standard set of interface types supported by the Vivado Design Suite.
These standard bus interfaces are defined on Xilinx IP cores, to enable easy it connection of the IP or block design to the board.
The list of available bus interface types can be found in the Vivado Design Suite installation: <install_location>/Vivado/ <version>/data/ip/interfaces
|Names the associated component from the <components> section.
|A brief description of the interface.
|4-position user DIP Switch
Lists the preferred IP to connect to, in VLNV (or VLN) format.
The version of the IP is not required as the Vivado tool will pick the latest version.
|vendor="xilinx.com" library="ip" name="axi_gpio" order="0"
|Specifies the priority of the preferred_ip for the interface. The priority counts down, with 0 being the highest priority.
|Specifies predefined configuration options for IP implementing the specified interface. Refer to Understanding Preset Files for more information.
|Maps the logical pins of an interface to the physical ports of the Xilinx device.
|See Port Map for details and examples.