You can functionally debug the design during the simulation verification process. Xilinx® provides a full design simulation feature in the Vivado® simulator. You can use the Vivado simulator to perform RTL simulation of your design. The benefits of debugging your design in an RTL-level simulation environment include full visibility of the entire design and the ability to quickly iterate through the design and debug cycle. For more information on how to configure and launch simulation, see the Vivado Design Suite User Guide: Logic Simulation (UG900).