- From the Flow Navigator under RTL Analysis, select Open Elaborated Design.
- Once the design has been elaborated, select Report
DRC from the Flow Navigator under RTL Analysis. Alternatively,
select . Note: Alternatively, you can enter this command in the Tcl Console:
report_drc -name <results_name>.
- In the Report DRC dialog box, set the
following options, and click OK:
Figure 1. Report DRC Dialog Box
- Results name
- Specify the name for the DRC results, which appear in a tab in the DRC window. Entering a unique name makes it easier to identify the results for a particular run during debug in the DRC window.
- Output file
- Optionally, specify a file name for the DRC results. To select a path other than the default, use the browse button.
- Interactive Report File
- Write the result in the Xilinx
RPX format to the specified filename. The RPX file is an interactive
report that contains all the report information and can be reloaded
into memory in the Vivado Design Suite using the
- Apply waivers
- Use the waivers you created to suppress
DRCs that you no longer want to view. For more
information, see this link in the
Design Suite User Guide: Design Analysis and Closure
Techniques (UG906).Note: Use the Display only waived violations to show just the waived violations in the Results window.
- Ignore all waivers
- Ignores the waivers you created.
- Rule Decks
- Specify a rule deck to run on the design. A rule
deck is a collection of design rule checks grouped for convenience.
During elaboration only the default rule deck is available. Other
rule decks are available at different stages of the FPGA design
flow, such as after synthesis or implementation.
- Runs a default set of checks recommended by Xilinx.
- Runs checks associated with logic optimization.
- Runs checks associated with placement.
- Runs checks associated with routing.
- Runs checks associated with bitstream generation.
- Runs checks associated with timing
constraints.Note: The timing_checks rule deck is not supported for elaborated designs.
- Checks validity of incremental ECO design modifications.
- Checks validity of engineering change
order (ECO) design modifications.Note: For elaborated designs, only the default rule deck is available.
- After specifying a rule deck, modify the rules to run as needed.