By default, the Vivado Design Suite automatically determines the top-level of the design hierarchy and the order of elaboration, synthesis, and simulation for source files added to the project. this can be controlled through the use of the Hierarchy Update settings in the right-click menu of the Sources Window. Refer to Hierarchy Update in Sources Window Commands in the Vivado Design Suite User Guide: Using the Vivado IDE (UG893) for more information.
The hierarchy of the design is displayed in the Hierarchy view of the Sources window. The compilation file order is displayed in the Compile Order view of the Sources window.
You can override the automatic determination of the top module by manually specifying the top of the design hierarchy. To specify the top module, select a module in the Sources window and select Set as Top from the right-click menu in the Hierarchy view of the Sources window.
When you change the top module, the Vivado IDE automatically reorders files in the Hierarchy and the Compile Order tabs of the Sources window according to the requirements of the new top module. Select Refresh Hierarchy from the right-click menu in the Sources window to reorder files based on changes to the source files.
You can override the automatic determination of the compile order using Hierarchy Update from the right-click menu command in the Sources window. You can specify the manual compile order mode by selecting or in the right-click menu of the Sources window. In manual mode, you can manually order files according to your own requirements. To manually order source files, select a file and drag it up or down in the file list order in the Compile Order view of Sources window. Alternatively, after selecting the file, use Move Up, Move Down, Move to Top, or Move to Bottom from the Sources window right-click menu.
To see a full list of the compile or evaluation order for all sources, use the
report_compile_order command in the Tcl Console. This command lists the order that files are compiled or evaluated for synthesis, implementation, and simulation. RTL compile order is listed for synthesis and simulation. Constraints evaluation order is listed for synthesis and implementation.