Xilinx System Generator for DSP is a design tool that combines RTL source files, Simulink and MATLAB software models, and C/C++ components of a DSP system into a single simulation and implementation environment. For more information on working with System Generator refer to the System Generator for DSP User Guide (UG634).
A System Generator design is often a sub-design that is incorporated into a larger HDL design. The recommended flow is to package the DSP module as an IP core in the Vivado Design Suite, to be added to the Xilinx IP catalog and integrated into any level of the design hierarchy as a sub-module as described in Working with IP Sources,or imported into the top-level of the design. This lets the Vivado IDE manage the project for the FPGA design, while handling the DSP module as an IP source that is developed and managed within System Generator. For more information see IP Catalog Compilation in the Vitis Model Composer User Guide (UG1483).