When using an IP that has already been synthesized, after implementation completes, the Implementation Completed dialog box opens to give you the option to open the implemented design, generate a bitstream, or view reports, as shown in the following figure.
Figure 1. Opening an Implemented IP
When performing timing analysis, the results are not accurate because the clocks are not yet routed and ideal clocks are used. This is most obvious when performing hold analysis, because the router cannot fix hold violations.
Some IP include the
HD.CLK_SRC property in the
<ip_name>_ooc.xdc file, which provides a location to a clock buffer and the SLEW timer models to improve the accuracy of post-implementation timing analysis.
Important: The implemented IP is for analysis only, and the results are not used or preserved during implementation of the top-level design. For information on module reuse and using an implemented version of the IP, see the Vivado Design Suite User Guide: Hierarchical Design (UG905).