The Vivado IDE manages both user-defined XDC timing and physical constraints for the entire design, as well as for Xilinx IP. It handles the association and the unification of constraints for Xilinx IP instantiated multiple times within a project.
Most IP in the IP catalog deliver IP-specific XDC constraints based on user customization. The constraints delivered by the IP are optimized using the default synthesis settings.
Do not change these settings for any of the IP design runs because you could
encounter issues with applying constraints. To take ownership of constraining an IP,
disable the XDC file(s) that are delivered with an IP. If you must change the
synthesis settings for an IP OOC run, you can use the following set_property command
in the Tcl console: set_property
<synthesis_option> <value> [get_runs
Tcl Command Example for Changing Synthesis Run Properties
set_property STEPS.SYNTH.DESIGN.ARGS.FSM_EXTRACTION sequential /
During design synthesis and implementation, the Vivado Design Suite processes the IP-delivered XDC constraints before processing the user-defined constraints, or after, depending on the constraint file.