Configuring I/O Ports - 2022.1 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

Document ID
UG899
Release Date
2022-05-04
Version
2022.1 English
Xilinx devices support configurable SelectIO™ interface drivers and receivers, which support various standard interfaces. These standard interfaces include programmable control of output strength and slew rate, on-chip termination using DCI, and generation of internal VREF. You can configure one or more I/O ports to define I/O standard, drive strength, slew type, pull type, and in term. This is useful for configuring ports that were imported from CSV or XDC files without the appropriate characteristics. Configure these ports to support the standards required for the system-level design. For example, you can combine some I/O standards within a single I/O bank but not others.
For information on standards and requirements for I/O banks, see the following, depending on your device:
  • 7 Series FPGAs SelectIO Resources User Guide (UG471)
  • UltraScale Architecture SelectIO Resources User Guide (UG571)
For information on packaging and pinout specifications, see the following, depending on your device:
  • 7 Series FPGAs Packaging and Pinout Product Specification (UG475)
  • UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification (UG575)
  • Zynq-7000 SoC Packaging and Pinout Product Specifications (UG865)

For detailed information on Zynq®-7000 pins, including MIO pins, see the Zynq-7000 SoC Technical Reference Manual (UG585).

For detailed information on Zynq UltraScale+ MPSoC pins, including MIO pins, see Zynq UltraScale+ Device Technical Reference Manual (UG1085).

To configure a port or a group of ports:

  1. In the I/O Ports window, select the ports.
  2. Right-click, and select Configure I/O Ports.
  3. In the Configure Ports dialog box (see the following figure), edit the following options, and click OK.
    Note: The Configure Ports dialog box options vary depending on the targeted device.
    I/O standard
    Select the I/O standard constraint. The tool does not check the I/O standard when it is assigned. You can assign any I/O standard to any port, but this might result in errors when running DRCs.
    Drive strength
    Select the drive strength value.
    Slew type
    Select the slew type value.
    Pull type
    Select the pull type value.
    PULLUP
    Applies a weak logic High level on a 3-stateable output or bidirectional port to prevent it from floating when not being driven.
    PULLDOWN
    Applies a weak logic Low level on a 3-stateable output or bidirectional port to prevent it from floating when not being driven.
    KEEPER
    Applies a weak driver on an 3-stateable output or bidirectional port to preserve its value when not being driven.
    NONE
    Does not apply a driver.
    Note: Alternatively, you can set the pull type constraint by clicking in the Pull Type column of the I/O Ports window.
    In Term type
    (7 series devices only) Define the parallel termination properties of the input signal. For more information, see the 7 Series FPGAs SelectIO Resources User Guide (UG471).
    ODT
    (UltraScale architecture-based devices only) Define the value of the on-die termination (ODT) at the input for both DCI and non-DCI versions of the standards supported. For more information, see the UltraScale Architecture SelectIO Resources User Guide (UG571).
    Fixed
    Indicates that the logical ports are user assigned. Ports must be fixed to ensure that the bitstream generates without errors.
    In the Configure Ports dialog box, the Fixed option is read only. To fix ports, select the ports in the I/O Ports window, right-click, and select Fix Ports, or enter the following Tcl command in the Tcl Console:
    set_property IS_LOC_FIXED true [get_selected_objects]
    Alternatively, you can enter the following Tcl command to fix ports:
    set_property IS_LOC_FIXED true [get_ports <list_of_ports>]


    CAUTION:
    For 7 series devices, Zynq-7000 SoC, Zynq UltraScale devices, UltraScale+ devices, and Zynq UltraScale+ MPSoCs, all I/O ports must have explicit values for the PACKAGE_PIN and IOSTANDARD constraints to generate a bitstream file. In the I/O Ports window, the word default is displayed in red to indicate that these values must be applied manually. You must apply extra care when assigning I/O standards, because these devices have Low and High voltage I/O banks.