architecture Memory IP enables configuration of DDR3 and DDR4
SDRAM, QDRIIPLUS SRAM, and RLDRAM3 type interfaces. As of 2015.3, the Memory IP has been
split into different IPs based on memory interface standards and tool flows. The
Customize IP dialog box contains basic and advanced configuration options that include
debug. Now that the memory I/O assignment process is consolidated with the rest of the
design, the IP configuration process is consistent with other Xilinx
IP. For more information on the IP configuration and management
process, see section "Creating a memory IP customization" in the
Vivado Design Suite User Guide: Designing with
the Memory IP in the Vivado tools:
- Open the Vivado IP catalog,
and expand the category.
- Double-click the desired interface to open the Customize IP
Although the I/O
Planning tab still exists in the Customize IP dialog box, it only explains the new
consolidated Memory IP I/O planning.
For information on configuring Memory IP, see the
Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide
Note: The Vivado Design Suite supports multiple UltraScale architecture memory controllers in the
same design. Each must be defined individually.