I/O Logic and Low-Speed I/O Planning‌ - 2022.1 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

Document ID
UG899
Release Date
2022-05-04
Version
2022.1 English

You can use the I/O Planning view layout in the Vivado IDE on elaborated, synthesized, and implemented designs. The view layout uses both Device and Package windows. Additional I/O information appears in the following windows: Clock Resources, Clock Regions, Package Pins, I/O Ports, Device Constraints, and Properties windows.

The Advanced I/O Planner is a new tool for Versal devices that allows you to place and move around I/O on a nibble and bank level granularity. Low speed I/O planning is done through the traditional design methodology as in I/O planning. For additional details on pin planning low speed I/O see Versal ACAP SelectIO Resources Architecture Manual (AM010).

Note: For more information on the windows in the Vivado IDE, see the Vivado Design Suite User Guide: Using the Vivado IDE (UG893).
Tip: When working with I/O planning projects, the I/O Planning view layout is called the Default Layout.

The I/O Planning view layout provides an interface to:

  • Create, import, and configure the initial list of I/O ports early in the design flow.
  • Perform final verification of the pinout at the end of the design flow.
  • Group related ports into interfaces, then assign them to package pins.
  • Use fully automatic pin placement or semi-automatic interactive modes for controlled I/O port assignment.
  • View the relationship of the physical package pins and banks with their corresponding I/O die pads.
  • Make informed decisions to optimize the connectivity between the PCB and the Xilinx® device.
  • Analyze the design and device I/O requirements.
  • Define an I/O pinout configuration or pinout that satisfies the requirements of both PCB and FPGA designs.