Because of the advanced capabilities of the Zynq® UltraScale+™ MPSoCs, the pin planning flow differs from other devices. You must go through IP customization for the Zynq UltraScale+ MPSoC IP to indicate the features you plan to use in your design. As you go through the design flow, the multiplexed I/O (MIO) pins do not show up in the user design or constraints. The I/O Planning Project does not show the utilization of the MIO ports, nor does it write out the placement for the MIO pins. The only way to see a full list of the used pins for a schematic or for communicating with the board designer, is by using the command to generate a CSV file. Xilinx recommends using an HDL project for all pin planning in Zynq UltraScale+ MPSoCs. For more information, see Defining and Configuring I/O Ports.