I/O and Clock Planning Stages‌ - 2022.1 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

Document ID
UG899
Release Date
2022-05-04
Version
2022.1 English

The Vivado Design Suite facilitates I/O and clock planning at different stages of the design process from initial collaboration between the PCB designer and the FPGA designer to validation of a fully implemented design. As the design progresses through the design flow, more information becomes available, which enables more complex analysis and rule checking. For example, analysis early in the design flow (synthesis/opt) uses actual cell delays but zero interconnect delay. Post place the cell delays are actual and interconnect delays are estimated, while the implemented design uses actual cell and interconnect delays for routed nets.

Proper I/O assignment depends on the structure of the FPGA, the requirements of the PCB design, and the interaction between the two. Visualizing how the FPGA interacts logically and physically with the PCB enables streamlining of the data flow through the device. I/O port assignment, which defines how signals from the PCB come into the FPGA design or go out to the board, and clock resource assignment, which defines the structure of the clock tree in the design, are often completed together.

For example, certain pins on the device are optimal for clock pins while others are optimal for digitally controlled impedance (DCI) cascade and internal voltage reference (VREF).

Failing to properly plan the I/O port and clock assignments can lead to decreased system performance, multiple design iterations, and longer design closure times. Versal clock and I/O design is easy with the Advanced I/O wizard setup I/O and clocking through a simple GUI. For information on board and device planning using the UltraFast™ design methodology, see this "Board and Device Planning" section in the UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949).

You can perform I/O planning at any stage in the design flow. For example, you can begin the I/O assignment process from a top-level ports list, a register transfer level (RTL) design, or a synthesized netlist. Various types of projects facilitate flexible entry points for I/O planning. Whenever possible, it is best to perform I/O assignment with a synthesized design. For example, you can only perform more complex I/O placement design rule checks (DRCs) on a synthesized design.

I/O Planning can be done in a number of different ways. After building a design in the Advanced I/O wizard, there is a new tool for Versal called "Advanced I/O Planner" that allows pin planning for any SelectIOor soft/hard memory interface on a bank (54 pins) and/or nibble level (6 pins) granularity. In the Advanced I/O Planner, you can autoplace your pin assignments, then adjust individual pin assignments through the classic pin planning tool. This tool can autoplace all the I/O interfaces to maximize the clocking and I/O architecture. If you need to place an individual I/O, the classic pin planning tools that write out pin constraints to an XDC file are still supported. Finally, you can also design your pin plan with a user-defined XDC file.

Certain types of IP, such as Memory IP, gigabit transceivers (GT), Xilinx® High Speed IO IP, PCI Express® (PCIe), and Ethernet interfaces have I/O ports associated with them. You must properly configure this IP using the IP capabilities in the Vivado Design Suite prior to beginning the I/O planning process. Because these interfaces are usually the most timing critical, use this IP as the starting point when considering the device pin assignments. In addition, use an RTL or synthesized design when using this IP. For details, see I/O and Clock Planning for IP with I/O Ports.