- In the Mem Byte Group column in the following figure, click the
drop-down list next to a bank.
- Select a signal group to assign.
After each assignment, the Vivado tools run active DRCs. DRC violations appear in red, and you can click the more info link for details. The Vivado IDE shows signal groups for each Memory IP in the design, so you can plan I/O assignments for multiple memory controllers at the same time.