Data Types Allowed on the Boundary of C and SystemVerilog

Data Types Allowed on the Boundary of C and SystemVerilog - 2022.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID

UG900

Release Date

2022-04-21

Version

2022.1 English

The IEEE Standard for SystemVerilog allows only subsets of C and SystemVerilog data types on the C and SystemVerilog boundary. Provided below are (1) details on data types supported in Vivado simulator and (2) descriptions of mapping between the C and SystemVerilog data types.