To run simulation of a synthesized or implemented design run the netlist generation process. The netlist generation Tcl commands can take a synthesized or implemented design database and write out a single netlist for the entire design.
The Vivado Design Suite generates a
netlist automatically when you launch the simulator using the IDE or the
Netlist generation Tcl commands can write SDF and the design netlist. The Vivado Design Suite provides the following Tcl commands:
write_verilog: Verilog netlist
write_vhdl: VHDL netlist
write_sdf: SDF generation