Power Analysis Using Vivado Simulator - 2022.1 English

The Switching Activity Interchange Format (SAIF) is an ASCII report that assists in extracting and storing switching activity information generated by simulator tools. This switching activity can be back-annotated into the Xilinx® power analysis and optimization tools for the power measurements and estimations.

Switching Activity Interchange Format (SAIF) dumping is optimized for Xilinx power tools and for use by the report_power Tcl command. The Vivado simulator writes the following HDL types to the SAIF file. Refer to this link in the Vivado Design Suite User Guide: Power Analysis and Optimization (UG907) for additional information.

• Verilog:
  • Input, Output, and Inout ports
  • Internal wire declarations
• VHDL:
  • Input, Output, and Inout ports of type std_logic, std_ulogic, and bit (scalar, vector, and arrays).
  Note: A VHDL netlist is not generated in the Vivado Design Suite for timing simulations; consequently, the VHDL sources are for RTL-level code only, and not for netlist simulation.

For RTL-level simulations, only block-level ports are generated and not the internal signals.

For information about power analysis using third-party simulation tools, see Dumping SAIF for Power Analysis, and Dumping SAIF in VCS in Simulating with Third-Party Simulators.