Preparing for Simulation - 2022.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2022-04-21
Version
2022.1 English

This chapter describes the components that you need when you simulate a Xilinx® device in the Vivado® Integrated Design Environment (IDE).

Set up the following before performing the simulation:

  • Create a test bench that reflects the simulation actions you want to run.
  • Set up an install location in Vivado IDE (if not using the Vivado simulator).
  • Compile your libraries (if not using the Vivado simulator).
  • Select and declare the libraries you need to use.
  • Specify the simulation settings such as target simulator, the simulation top module name, top module (design under test), display the simulation set, and define the compilation, elaboration, simulation, netlist, and advanced options.
  • Generate a Netlist (if performing post-synthesis or post-implementation simulation).