Running Functional Simulation - 2022.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2022-04-21
Version
2022.1 English

Post-Synthesis Functional Simulation

You can view Run Simulation > Post-Synthesis Functional Simulation option (shown in the previous figure) after completing a successful synthesis run.

After synthesis, the general logic design has been synthesized into device-specific primitives. Performing a post-synthesis functional simulation ensures that any synthesis optimizations have not affected the functionality of the design. After you select a post-synthesis functional simulation, the functional netlist is generated, and the UNISIM libraries are used for simulation.

Post-Implementation Functional Simulations

The Run Simulation > Post-Implementation Functional Simulation option (shown in the previous figure) becomes available after completing implementation run.

After implementation, the design has been placed and routed in hardware. A functional verification at this stage is useful in determining if any physical optimizations during implementation have affected the functionality of your design.

After you select a post-implementation functional simulation, the functional netlist is generated and the UNISIM libraries are used for simulation.