Running Timing Simulation - 2022.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2022.1 English
Tip: Post-Synthesis timing simulation uses the estimated timing delay from the device models and does not include interconnect delay. Post-Implementation timing simulation uses actual timing delays.

When you run Post-Synthesis and Post-Implementation timing simulation the simulator tools include:

  • Gate-level netlist containing SIMPRIMS library components
  • Standard Delay Format (SDF) files

You defined the overall functionality of the design in the beginning. When the design is implemented, accurate timing information is available.

To create the netlist and SDF, the Vivado Design Suite:

  • Calls the netlist writer, write_verilog with the -mode timesim switch and write_sdf (SDF annotator)
  • Sends the generated netlist to the target simulator

You control these options using Simulation Settings as described in Using Simulation Settings.

Important: Post-Synthesis and Post-Implementation timing simulations are supported for Verilog only. There is no support for VHDL timing simulation. If you are a VHDL user, you can run post synthesis and post implementation functional simulation (in which case no SDF annotation is required and the simulation netlist uses the UNISIM library). You can create the netlist using the write_vhdl Tcl command. For usage information, refer to the Vivado Design Suite Tcl Command Reference Guide (UG835).
Important: The Vivado simulator models use interconnect delays; consequently, additional switches are required for proper timing simulation, as follows: -transport_int_delays -pulse_r 0 -pulse_int_r 0

Post-Synthesis Timing Simulation

The Run Simulation > Post-Synthesis Timing Simulation option (shown in the previous figure) becomes available after completing a successful synthesis run.

After synthesis, the general logic design has been synthesized into device-specific primitives, and the estimated routing and component delays are available. Performing a post-synthesis timing simulation allows you to see potential timing-critical paths prior to investing in implementation. After you select a post-synthesis timing simulation, the timing netlist and the estimated delays in the SDF file are generated. The netlist files includes $sdf_annotate command so that the simulation tool includes the generated SDF file.

Post-Implementation Timing Simulations

The Run Simulation > Post-Implementation Timing Simulation option (shown in the previous figure) becomes available after completing implementation run.

After implementation, the design has been implemented and routed in hardware. A timing simulation at this stage helps determine whether or not the design functionally operates at the specified speed using accurate timing delays. This simulation is useful for detecting unconstrained paths, or asynchronous path timing errors, for example, on resets. After you select a post-implementation timing simulation, the timing netlist and the SDF file are generated. The netlist files includes $sdf_annotate command so that the generated SDF file is picked up.

When you specified simulation settings, you specified whether or not to create an SDF file and whether the process corner would be set to fast or slow.

Tip: To find the SDF file optional settings, in the Vivado IDE Flow Navigator, right click Simulation and select Simulation Settings. In the Settings dialog box, select Simulation category and click Netlist tab.

Based on the specified process corner, the SDF file contains different min and max numbers.

Run two separate simulations to check for setup and hold violations.

To run a setup check, create an SDF file with -process_corner slow, and use the max column from the SDF file.

To run a hold check, create an SDF file with the -process_corner fast, and use the min column from the SDF file. The method for specifying which SDF delay field to use is dependent on the simulation tool you are using. Refer to the specific simulation tool documentation for information on how to set this option.

To get full coverage run all four timing simulations, specify as follows:

  • Slow corner: SDFMIN and SDFMAX
  • Fast corner: SDFMIN and SDFMAX