SECUREIP Simulation Library - 2022.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2022.1 English

Use the SECUREIP library for functional and timing simulation of complex device components, such as GT.

Note: Secure IP Blocks are fully supported in the Vivado simulator without additional setup.

Xilinx leverages the encryption methodology as specified in the IEEE standard Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP) (IEEE-STD-P1735). The library compilation process automatically handles encryption.

Note: See the simulator documentation for the command line switch to use with your simulator to specify libraries.

The following table lists special considerations that must be arranged with your simulator vendor for using these libraries.

Table 1. Special Considerations for Using SECUREIP Libraries
Simulator Name Vendor Requirements
Siemens EDA ModelSim SE Siemens If design entry is in VHDL, a mixed language license or a SECUREIP OP is required. Contact the vendor for more information.
Siemens EDA Questa Advanced Simulator
VCS Synopsys  
Active-HDL Aldec If design entry is VHDL, a mixed language license is required.
Important: See Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973) for the supported version of third-party simulators.


The UNISIM library contains the wrappers for VHDL SECUREIP. Place the following two lines at the beginning of each file so that the simulator can bind to the entity:

Library UNISIM;

Verilog SECUREIP Library

When running a simulation using Verilog code, you must reference the SECUREIP library for most simulators.

If you use the precompiled libraries, use the correct directive to point to the precompiled libraries. The following is an example for the Vivado simulator:

Important: You can use the Verilog SECUREIP library at compile time by using -f switch. The file list is available in the following path: <Vivado_Install_Dir>/data/secureip/secureip_cell.list.f.