The configuration simulation models (
SIM_CONFIGE3) with an instantiation template allow supported
configuration interfaces to be simulated to ultimately show the
DONE pin going HIGH. This is a model of how the supported
devices react to stimulus on the supported configuration interface.
The following table lists the supported interfaces and devices.
|7 series and Zynq®-7000 SoC Devices||Yes||Yes||No||No|
|UltraScale+™ ™ Devices||Yes||Yes||No||No|
The models handle control signal activity as well as bit file downloading. Internal
register settings such as the
status registers are included. You can monitor the Sync Word as it enters the device
and the start-up sequence as it progresses. The following figure illustrates how the
system should map from the hardware to the simulation environment.
The configuration process is specifically outlined in the configuration user guides for each device. These guides contain information on the configuration sequence, as well as the configuration interfaces.
System Level Description
The configuration models allow the configuration interface control logic to be tested before the hardware is available. It simulates the entire device, and is used at a system level for:
- Applications using a processor to control the configuration logic to ensure proper wiring, control signal handling, and data input alignment.
- Applications that control the data loading process with the CS (SelectMAP Chip Select) or CLK signal to ensure proper data alignment.
- Systems that need to perform a SelectMAP
The config_test_bench.zip file has sample test benches that simulate a processor running the SelectMAP logic. These test benches have control logic to emulate a processor controlling the SelectMAP interface, and include features such as a full configuration, ABORT, and Readback of the IDCODE and status registers.
For the ZIP files associated with this model, see Xilinx Answer Record 53632.
The simulated host system must have a method for file delivery as well as control signal management. These control systems should be designed as set forth in the device configuration user guides.
The configuration models also demonstrate what is occurring inside the device during the configuration procedure when a BIT file is loaded into the device.
During the BIT file download, the model processes each command and changes registers settings that mirror the hardware changes.
You can monitor the CRC register as it actively accumulates a CRC value. The model also shows the Status Register bits being set as the device progresses through the different states of configuration.
Debugging with the Model
Each configuration model provides an example of a correct configuration. You can leverage this example to assist in the debug procedure if you encounter device programming issues.
You can read the Status Register through JTAG using the Vivado Device Programmer tool. This register contains information relating to the current status of the device and is a useful debugging resource. If you encounter issues on the board, reading the Status Register in Vivado Device Programmer is one of the first debugging steps to take.
After the status register is read, you can map it to the simulation to pinpoint the configuration stage of the device.
For example, the
GHIGH bit is set HIGH after the data load process
completes successfully; if this bit is not set, then the data loading operation did
not complete. You can also monitor the
DONE signals set in BitGen that are released in the start-up
The configuration models also allow for error injection. The active CRC logic detects any issue if the data load is paused and started again with any problems. It also detects bit flips manually inserted in the BIT file, and handles them just as the device would handle this error.
Each device-specific configuration user guide outlines the supported methods of interacting with each configuration interface.The table below shows which features discussed in the configuration user guides are supported.
- Does not support Readback of configuration data.
- Does not store configuration data provided, although it does calculate a CRC value.
- Can perform Readback on specific registers only to ensure that a valid command sequence and signal handling is provided to the device.
- Is not intended to allow Readback data files to be produced.
Table 2. Model-Supported Slave SelectMAP and Serial Features Slave SelectMAP and Serial Features Supported Master mode No Daisy chain - slave parallel daisy chains No SelectMAP data loading Yes Continuous SelectMAP data loading Yes Non-continuous SelectMAP data loading Yes SelectMAP
Yes SelectMAP reconfiguration No SelectMAP data ordering Yes Reconfiguration and MultiBoot No Configuration CRC—CRC checking during configuration Yes Configuration CRC—post-configuration CRC No