Setting the Simulation Runtime Resolution - 2022.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2022-04-21
Version
2022.1 English

Set the simulation run-time resolution using `timescale in test bench. There is no simulator performance gain achieved through use of coarser resolution with the Xilinx simulation models. (In Xilinx simulation models, most simulation time is spent in delta cycles, and delta cycles are not affected by simulator resolution.)

Important: Run simulations using a time resolution of 1 fs. Some Xilinx primitive components, such as GT, require a 1 fs resolution to work properly in either functional or timing simulation.

See Simulation Options for detailed information on Simulation Options in Settings dialog box.

Important: Picoseconds are used as the minimum resolution because testing equipment can measure timing only to the nearest picosecond resolution.