Simulating with Vivado Simulator - 2022.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2022-04-21
Version
2022.1 English

The Vivado simulator is a Hardware Description Language (HDL) event-driven simulator that supports functional and timing simulations for VHDL, Verilog, SystemVerilog (SV), and mixed VHDL/Verilog or VHDL/SV designs.

The Vivado simulator supports the following features:

  • Source code debugging (step, breakpoint, current value display)
  • SDF annotation for timing simulation
  • VCD dumping
  • SAIF dumping for power analysis and optimization
  • Native support for HardIP blocks (such as serial transceivers and PCIe┬« )
  • Multi-threaded compilation
  • Mixed language (VHDL, Verilog, or SystemVerilog design constructs)
  • Single-click simulation re-compile and re-launch
  • One-click compilation and simulation
  • Built-in support for Xilinx simulation libraries
  • Real-time waveform update

See the Vivado Design Suite Tutorial: Logic Simulation (UG937) for a step-by-step demonstration of how to run Vivado simulation.